Content addressable memory (CAM) devices are often used in network switching and routing systems to determine forwarding destinations and permissions for data packets. A CAM device can be instructed to compare search data obtained from an incoming packet with contents of a forwarding or classification database stored in an associative storage array within the CAM device. If the search data matches an entry in the database, the CAM device generates a match address that corresponds to the location of the matching entry, and asserts a match flag to signal the match. The match address is then typically used to address another storage array, either within or separate from the CAM device, to retrieve a forwarding address or other routing information for the packet.
The associative storage array of a CAM device, a CAM array, is typically populated with CAM cells arranged in rows and columns. Precharged match lines are coupled to respective rows of the CAM cells, and bit line pairs and compare line pairs are coupled to respective columns of the CAM cells. Together, the bit line pairs form a data port for read and write access to address-selected rows of CAM cells, and the compare line pairs form a compare port for inputting search data to the CAM array during search operations. The CAM cells themselves are specialized store-and-compare circuits each having a storage element to store a constituent bit of a database entry, referred to herein as a CAM word, and a compare circuit for comparing the stored bit with a search bit presented on the compare lines. In a typical arrangement, the compare circuits within the CAM cells of a given row are coupled in parallel to the match line for the row, with each compare circuit switchably forming a discharge path to discharge the match line if the stored bit and search bit do not match. By this arrangement if any one bit of a CAM word does not match the corresponding bit of the search data, the match line for the row is discharged to signal the mismatch. If all the bits of the CAM word match the corresponding bits of the search data, the match line remains in its precharged state to signal a match. Because search data is presented to all the rows of CAM cells in each compare operation, a rapid, parallel search for a matching CAM word is performed.
FIG. 1 illustrates a prior-art arrangement of compare lines (CL and /CL) and bit lines (BL and /BL), and their interconnection to a corresponding column of CAM cells 101. The bit lines and compare lines each extend along the length of the column of CAM cells and are used to conduct complementary data signals, D and /D, and search signals, C and /C, respectively. The data signals D and /D represent a data bit (D) being written into or read from the data storage element 109 of an address-selected one of the CAM cells 101 during a read or write operation. Search signals C and /C are driven onto the compare lines during a search operation and represent a search bit (referred to herein as a comparand bit, C) to be compared with the data bit stored within each CAM cell 101 via a compare circuit 111.
In the high-density CAM arrays prevalent in modern devices, the compare lines and bit lines typically extend side by side in close proximity across hundreds or thousands of rows of CAM cells and therefore exhibit a substantial parasitic capacitance as shown in FIG. 1. As a result, high frequency search signals driven onto the compare lines tend to propagate through the parasitic capacitance onto the bit lines, and therefore may interfere with data access operations. More specifically, capacitively-coupled transients resulting from charging compare lines may destructively interfere with the relatively small swing differential data signals generated on the bit lines during data read operations, potentially causing an incorrect data state to be read. Such interference is referred to herein as search-read interference.
FIG. 2 illustrates the search-read interference phenomenon in the context of FIG. 1. At time T1, a word line is activated to enable access to one of CAM cells 101, thereby enabling the contents of the data storage element 109 onto the bit lines, BL and /BL. As shown, the bit lines are initially precharged so that, at T1, one of the bit lines (whichever is to carry a logic low signal) begins to be discharged by the low output of the data storage element 109, thus developing a differential potential 118 on the bit lines. In the absence of search-read interference, the differential potential eventually settles to nominal level so that, when a sense amp strobe signal (SAS) is asserted at time T3, a sense amplifier is enabled to amplify the differential bit line potential to a logic level signal that may be captured in downstream logic. Turning to the search operation, a comparand bit is driven onto the compare lines CL and /CL starting at time T2. If the charging compare line is adjacent the discharged bit line (i.e., CL charged and /BL discharged, or /CL charged and BL discharged), then the high-going search signal propagates through the parasitic capacitance (i.e., is capacitively coupled) to the discharged bit line and produces a transient, upward-spiking signal level 120 on the bit line. The resulting loss of differential signal amplitude on bit lines BL and /BL represents a substantial signal degradation and, if the sense amp strobe signal is raised at time T3, may cause the sense amplifier to output an incorrect data state.
One solution to the search-read interference problem is to delay assertion of the sense amp strobe signal until a later time, T4, after the capacitively coupled transient has settled (shown in dashed outline in FIG. 2). Unfortunately, delaying assertion of the sense amp strobe signal directly increases the read cycle time and may detrimentally affect other aspects of device or system operation. Also, as search rates increase in future CAM generations, the shrinking time between search operations may leave insufficient time for capacitively coupled transients to settle.